W25Q64BVSFIG【PDF 2/61 页】IC SPI FLASH 64MBIT 16SOIC

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W25Q64BV

Table of Contents

1.

2.

3.

4.

5.

6.

7.

8.

GENERAL DESCRIPTION ............................................................................................................... 5

FEATURES....................................................................................................................................... 5

PIN CONFIGURATION SOIC 208-MIL ............................................................................................ 6

PAD CONFIGURATION WSON 8X6-MM ........................................................................................ 6

PAD CONFIGURATION PDIP 300-MIL ........................................................................................... 7

PIN DESCRIPTION SOIC 208-MIL, PDIP 300-MIL AND WSON 8X6-MM...................................... 7

PIN CONFIGURATION SOIC 300-MIL ............................................................................................ 8

PIN DESCRIPTION SOIC 300-MIL .................................................................................................. 8

8.1

8.2

8.3

8.4

8.5

8.6

Package Types..................................................................................................................... 9

Chip Select (/CS).................................................................................................................. 9

Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) .................................... 9

Write Protect (/WP)............................................................................................................... 9

HOLD (/HOLD) ..................................................................................................................... 9

Serial Clock (CLK) ................................................................................................................ 9

9.

10.

BLOCK DIAGRAM.......................................................................................................................... 10

FUNCTIONAL DESCRIPTION ....................................................................................................... 11

10.1

SPI OPERATIONS ............................................................................................................. 11

10.1.1

10.1.2

10.1.3

10.1.4

Standard SPI Instructions...................................................................................................11

Dual SPI Instructions ..........................................................................................................11

Quad SPI Instructions.........................................................................................................11

Hold Function .....................................................................................................................11

10.2

WRITE PROTECTION ....................................................................................................... 12

10.2.1

Write Protect Features........................................................................................................12

11.

CONTROL AND STATUS REGISTERS ........................................................................................ 13

11.1

STATUS REGISTER .......................................................................................................... 13

11.1.1

11.1.2

11.1.3

11.1.4

11.1.5

11.1.6

11.1.7

11.1.8

BUSY..................................................................................................................................13

Write Enable Latch (WEL) ..................................................................................................13

Block Protect Bits (BP2, BP1, BP0)....................................................................................13

Top/Bottom Block Protect (TB)...........................................................................................13

Sector/Block Protect (SEC) ................................................................................................13

Status Register Protect (SRP1, SRP0)...............................................................................14

Quad Enable (QE) ..............................................................................................................14

Status Register Memory Protection ....................................................................................16

11.2

INSTRUCTIONS................................................................................................................. 17

11.2.1

11.2.2

Manufacturer and Device Identification ..............................................................................17

Instruction Set Table 1........................................................................................................18

-2-

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